The present invention relates to a method of manufacturing a resin encapsulated semiconductor device.
Of resin encapsulated semiconductor devices which are now in widespread use, a package form called "LGA" (Land Grid Array) is known.
In this type of LGA package, bumps or protruding electrodes are respectively provided over electrode pads which exit on a semiconductor element or chip. Inner pads are provided over a substrate (body portion) comprised of an insulated board such as a printed wiring board made up of a copper-clad laminate or the like, and the protruding electrodes are connected to their corresponding inner pads.
As methods of forming such protruding electrodes, there have been widely adopted a method of effecting plating processing using gold, solder or the like in a final stage of a wafer process generally called "bump", a method of forming balls according to an ultrasonic-combined thermo-compression system or the like, etc.
Further, a metal bonding method using high-temperature processing or a resin-based bonding method, etc. have been widely used for connecting the bumps formed in this way and the inner pads on the substrate respectively. However, there is known a case in which since portions at which the semiconductor chip, substrate and bumps are bonded to one another, are different in thermal expansion coefficient from one anther in a state in which the above way is kept intact, a bonding property might be degraded due to a thermal cycle at an operating environment.
As countermeasures against such a case, a method of charging a resin such as a liquid thermosetting epoxy resin between the semiconductor chip and the substrate has been widely used to improve product quality such as a bonding property, moisture resistance, etc.
Connecting pads printed on the back of the substrate in advance are provided as external connecting terminals [When solder balls are further connected to the connecting pads respectively, a package form called "BGA" (Ball Grid Array) is obtained, which is now widely adopted].
It is also needless to say that the inner pads and connecting pads are electrically connected to one another within the substrate by wires or interconnections and through holes or the like.
As has already been known to date, a size reduction in electronic equipment has been advanced in recent years. Therefore, there is a strong demand for a possible reduction in the outside size of a package mounted on a semiconductor chip. The present package might be generically called "CSP" [Chip Size (or Scale) Package].
It becomes also necessary to reduce the distance between an end surface of the substrate and an end surface of the semiconductor chip or make them flush with each other.
As its corresponding countermeasures, a plurality of bumps or protruding electrodes provided on individually-divided semiconductor chips are normally respectively bonded to inner pads on substrates provided in frame form singly or plurally by the aforementioned method, and a resin is charged between the substrate and each semiconductor chip.
As a method of charging the resin therebetween, a method of dropping a resin by a dispense system and filling with it by a widely known capillary phenomenon has been adopted. Described specifically, when a resin to be charged is dropped onto a substrate by a dispenser, the resin is charged into a clearance between the substrate and a semiconductor chip by the capillary phenomenon, thus leading to completion of a package form.
However, the above-described conventional method involves the following problems upon a reduction in package.
In the dispense system described above, the substrate is mostly set larger than the semiconductor chip in size by about 0.1 mm to 0.3 mm in order to improve workability thereof at the filling of the resin. As a result, the substrate is not completely coincident in size with the semiconductor chip, thus making it impossible to fully meet a demand for a size reduction in most cases. Further, processing such as cutting might be adopted after the filling of the resin to make the substrate and the semiconductor chip coincident in size with each other. However, this has led to a factor in cost-up.